[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #85 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #84)

> i just realised, through writing this out (which is always good) that the
> above isn't strictly true.  we do actually need 1 bit to tell us that the
> next instruction is back to "32 bit mode".

i also just realised that in proposal v2 encoding, the 8bit nop is likewise the
FSM  "return to 32bit mode" indicator that has a knock-on (chain) effect on
subsequent instructions.

however - i stress and emphasise: adding the 16+16-immed/reg encoding turns
what would otherwise be a dead-straight "is there an 8bit nop pattern"
detection into a far more complex system that's already borderline.

sigh i wish OpenPOWER had been designed with 16bit in mind right from the
start.

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