[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #64 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://ftp.libre-soc.org/20201123_232927.jpg

one set of cables connected to STLINKv2

one set of cables connected to VERSAECP5/ULX3S

therefore *three separate tables* plus, later on, explicit instructions,
"connect each coloured male jumper to each coloured female jumper"

this way you do not lose the connections when you want to disconnect and store
the two devices.

the FPGA should have the female-female jumpers so that the wires do not
randomly damage the bare PCB due to a short.

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