[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Nov 23 23:35:47 GMT 2020


--- Comment #64 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---

one set of cables connected to STLINKv2

one set of cables connected to VERSAECP5/ULX3S

therefore *three separate tables* plus, later on, explicit instructions,
"connect each coloured male jumper to each coloured female jumper"

this way you do not lose the connections when you want to disconnect and store
the two devices.

the FPGA should have the female-female jumpers so that the wires do not
randomly damage the bare PCB due to a short.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-soc-bugs mailing list