[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #61 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #60)
> (In reply to Cole Poirier from comment #59)
> 
> > Break it down even further into one table for each fpga wiring, and a shared
> > table for wiring those colours to the STLINKv2?
> 
> if you review the cabling for the VERSAECP5 you'll find that that is exactly
> what i have done.  do you see a separate STLINKV2 cable picture for the
> VERSAECP5?

No actually I don't see it. I see a picture of the Versa ECP5 with colored
circles and numbers, and I see the lattice table 12 with coloured squares
representing the wires next to the pin numbers, as well as the "viewed from
above PCB" diagram of the STLINKv2, and the corresponding table again with
colours representing the wires next to the pin numbers. I don't see anything
missing. I'm confused.

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