[Libre-soc-bugs] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #69 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cesar Strauss from comment #68)
> (In reply to Luke Kenneth Casson Leighton from comment #67)
> > out of curiosity, given the subject of this bugreport: is testing of
> > operations that are zero for A included? :)  actually this is more for the
> > PowerDecoder2 (or sub-decoders), now.
> 
> Not yet, but it will be.

fantastic.

> For simplicity, I began with the Shifter, that doesn't have either "zero A"
> or immediates. But I really will implement these next, for the ALU test case.

great to hear, this will confirm the low level

i wonder... although the CompUnit itself needs zero-immediate tests, to make
sure it can cope at the low level, really, we also need actual unit tests
(test_*_compunit.py) at the level up.

for the low-level that you are doing (which is equally as important), it does
not interact with PowerDecoder2.

the Op Subset Record is given to CompUnit *by* PowerDecoder2, and it is
PowerDecoder2 which analyses the instruction and identifies whether the
register is RA or RA-or-Zero.

that interaction is what also needs testing: a nonzero value placed into the
regfile, use RA-or-Zero, have PowerDecoder2 decode that, and confirm that zero
was passed as the operand.

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