[Libre-soc-bugs] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=336

--- Comment #66 from Cesar Strauss <cestrauss at gmail.com> ---
I've finished the CompUnit parallel test for the Shifter. Next, I'll port the
ALU tests, followed by the Load / Store CompUnit. 

It features:

1) Operands can arrive in any order, or simultaneously

Simulated delays are specified per port.

2) Results (if multiple) can also be accepted in any order

3) Results are checked as they are produced

4) Detects duplicated or missing operand requests or results

A running transaction counter is maintained at each port. As busy is negated,
all counters must match.

To see:

1) Update nmutil, to get the latest write_gtkw functionality

2) Run:

$ python ~/src/soc/src/soc/experiment/test/test_compalu_multi.py 

$ gtkwave ~/test/soc/test_compunit_fsm1.gtkw 

There are three transactions, and each time the order of arrival of operands
varies.

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