[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #29 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #23)
> | 0 | 1  | 2 3 4 | | 567.8 | 9ab  | c d e | f |
> | 1 | o2 |  RT   | | 010.0 | RB|0 | offs  | 1 | addi.
> | 1 | o2 |  RT   | | 010.1 | RB|0 | offs  | 1 | addis.
> 
> these i'm reluctant to go entirely immediate in bits 2-4 because when
> RB=0 it encodes "li RT, #imm" even though the immediate is only in
> the range 0-15 for addi and -8 to 7 for addis.

I'd recommend not supporting addis for 16-bit mode since most of the time addis
is part of a addi addis sequence to add a 32-bit constant (usually some
variable/function's address). That constant would almost always not fit in
whatever reduced-range immediate you have available in 16-bit mode.

> (actually a better encoding there would be just addis, why has nobody
> noticed a massive overlap between addis and addi before in OpenPOWER
> ISA v3.0B????)

addis adds bits right above the bits you can specify with standard 32-bit addi.
together they allow you to add an arbitrary 32-bit constant.

This is kinda like lui/addi on RISC-V.

-- 
You are receiving this mail because:
You are on the CC list for the bug.