[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #8)

> if those pages could be specified even at the 10-bit level that's where
> an overhead of the use of 16 bits becomes worth it, because the chances
> of needing context-relevant opcodes (heavy FP computation, or heavy
> Video computation) become much higher.

e.g. use the 10-bit mode to swap out the entirety of FP and replace them with
YUV2RGB and DCT etc. etc. opcodes, even those needed just to hyper-optimise an
inner loop.

(In reply to Jacob Lifshay from comment #4)
> (In reply to Luke Kenneth Casson Leighton from comment #3)
> > hm hm fmr explicitly requires 2 registers (src, dest).  in 10-bit mode
> > there's
> > so little space that the only possible candidate for dropping and replacing
> > with fmr. would be fmul.
> 
> Will require some thought.

in 16-bit mode there's a spare pair of bit (0-1).  one of those - and i stress
that this can only be done in 16-bit mode not 10-bit mode - can be used to
select alternative meanings.

* bit 1=0 - opcode is fmul.  bit 1=0 - opcode is fdiv
* bit 1=0 - opcode is fabs.  bit 1=0 - opcode is fmr

(In reply to Jacob Lifshay from comment #2)

> An additional idea, if we have to use an additional 16-bit instruction to
> enter 16-bit mode: it's common to have just 1 32-bit (or wider) instruction
> in a sequence of 16-bit instructions, it might be a good idea to have a
> limited subset of 16-bit instructions have additional info included to tell
> the processor to exit 16-bit mode for just 1 instruction, then reenter
> 16-bit mode without needing to use an enter-16-bit-mode instruction.

in 16-bit mode, bit 15 plus bit 0 can be used to indicate this change-over.
however fascinatingly there are still some combinations left:

* 0:f = 0b01: stay in 16-bit mode
* 0:f = 0b00: leave 16-bit mode permanently
* 0:f = 0b10: leave 16-bit mode for one cycle
* 0:f = 0b11: free to use for something completely different.

perhaps that could be used to redefine the [entire] opcode space to
"immediate" variants?  addi, addis, mulli, ori etc.

or, another alternative: add one extra bit to all registers, switching
to a high bank (r8-r15)

my feeling is that immediate-variants of a few select instructions
(including branch-conditional) would have a higher bang-per-buck

the only thing to watch out for here: this is getting pretty complex.

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