[Libre-soc-bugs] [Bug 238] POWER Compressed Formal Standard writeup

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=238

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ideas currently are to move "into" 16-bit mode by way of 2 major opcodes,
and to remain there as long as bit 15 is "1".  however when transitioning
"into" 16-bit mode, that leaves 11 bits (actually 10 excluding the "remain
in C mode" bit) which could be used for actual instructions.

by cutting back on functionality (and register range) in 10-bit mode then
extending the register range with the remaining 5 bits it seems to result
in a reasonably comprehensive compressed ISA.

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