[Libre-soc-bugs] [Bug 526] create dry-run 180nm GDS-II files for IMEC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=526

--- Comment #27 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #24)
> with commit db5f3c203190f110be02cb12ff107f206528ac9b i finally have the
> (dummy, hand-edited) ls180.vst compiling, currently running cougar on
> a 25,000 sized layout is taking a loooong time.
> 
> however there were no prior errors (including the ones i turned from errors
> to warnings) so i expect this run to succeed.
> 
> i will know tomorrow and will try with the litex peripherals and the core.

Can you commit the new hand-edited ls180.vst, currently when running build.sh
in experiments9 I get the same error as earlier. Once that's fixed, mine will
hopefully compile much faster than yours since I'm not limiting my cpu clock to
1 GHz.

```
Connect pad contact <id:8732 Pin vss METAL3 [460.L 0.L] 403.L x 4.L vss.3
SOUTH>
    HORIZONTAL rail.
    railRange:[2, 3, 4, 5, 6, 7]
    Connect to [-2] @298.L
    Try to connect to: <HorizontalRail "vdd" (2) @298.L>

[ERROR] <id:8732 Pin vss METAL3 [460.L 0.L] 403.L x 4.L vss.3 SOUTH> is outside
rail/corona X range,
        power pad is likely to be to far off west or east.
        (core:<Box 464.L 394.L 25476.L 25406.L>)
        Python stack trace:
        #0 in                  __init__() at
.../lib64/python2.7/dist-packages/crlcore/helpers/io.py:167
        #1 in                   connect() at
.../dist-packages/cumulus/plugins/alpha/chip/corona.py:120
[snip]
        #9 in                  <module>() at
.../coriolis-2.x/Linux.x86_64/Release.Shared/install/bin/cgt:204

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