[Libre-soc-bugs] [Bug 528] New: parameter needed in coriolis2 to specify individually which clocks are to have a Clock Tree

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=528

            Bug ID: 528
           Summary: parameter needed in coriolis2 to specify individually
                    which clocks are to have a Clock Tree
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Hardware Layout
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-bugs at lists.libre-soc.org
   NLnet milestone: ---

currently in the new niolib plugin the assumption is that all clocks which
are given separate domains (and therefore separate IO Rings) will be external
and therefore require a global H Clock Tree to cover the entire ASIC

https://bugs.libre-soc.org/show_bug.cgi?id=155#c24

if we have an external 24mhz Reference Clock, we do not actually want
this to result in a full global H-Clock Tree covering the entire ASIC.

the only place we want it to go is: to the PLL block.

however it is the *output* from the PLL that we want to have a global H-Clock
Tree.

but, given that this could run as high as 300 mhz we do *NOT* want it to
go out as an external pin.

bottom line is that we need to be able to specify, as a coriolis2/settings.py
configuration parameter, exactly which clocks are to have an H-Tree created
for them.

not for the assumption to be that if it is a clock, and it is on the IORing,
it *must* have an H-Tree.

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