[Libre-soc-bugs] [Bug 155] a PLL is needed for the SoC

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=155

--- Comment #21 from Staf Verhaegen <staf at fibraservi.eu> ---
A little over a week ago me, Dimitri and Marie-Minerve from LIP6 had a call to
discuss the PLL design for the Libre-SoC. We propose to only use power of two
for the division in the PLL so just flip-flops can be used for it. See also
https://en.wikipedia.org/wiki/Frequency_divider This is what we propose for the
pin-out o the PLL:

* The refclk signal is the external clock signal.
* One external signal vcodiv that selects between having the VCO oscillating at
16x or 8x the reference clock.
* Two signals clksel to select between four signals to use for the SoC clock:
the reference clock (e.g. bypass PLL), VCO/2, VCO/4 and VCO/8.
* One external digital output VCOd16 that is VCO/16
* One analog output, likely the voltage for VCO.
* Current design has not lock signal, Dimitri will see if he can provide that.
If so it will also be an external digital output.

Dimitri will see if he can tune the PLL so there is a factor of two between the
maximum and minimum oscillation frequency of the VCO. This way one could in
theory reach any clock frequency for the SoC between fVCOmax/2 and fVCOmin/8 by
playing with frequency of reference clock and the clock division.

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