[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #48 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
cole check the wires into the STLinkV2 compared to where the "slot" is, you'll
find you have the connector rotated 180 degrees

https://libre-soc.org/HDL_workflow/ECP5_FPGA/

-- 
You are receiving this mail because:
You are on the CC list for the bug.