[Libre-soc-bugs] [Bug 517] Define JTAG pins and set up with litex for ulx3s85f

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=517

--- Comment #44 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #43)
>
> *click* right.  ok.  so the answer to that can be deduced from the
> schematic, and from the net names.  you'll see that both pin1 and pin2 of
> that connector, they're both connected to 3.3v, yes?  so the voltage is
> going to be the same, therefore there's no need to connect 2 wires to that
> same voltage unless there are two separate locations to put it.
> 
> given that the STLinkv2 only has the one input MCU-VDD, you can't put the
> 2nd wire anywhere, can you?

Aha!! Yes now it's clicked for me, the pin labels for the stlinkv2 show that
pin1 and pin2 are for the same MCU-VDD signal, not two separate ones.

> the only reason you might want 2 wires is if the current carrying capacity
> of 1 is too low.  and that's not the case here.

Ahhh, makes sense.

Ok, so I'm going to keep pin2 instead of pin1 cause they're next to each other
on the stlinkv2 rather than diagonal to each other. It's pretty arbitrary but I
think this will be slightly easier in my mind.

I'll create the wiki page now.

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