[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=70

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #11)
> discovered that there are already quite a few protocols that are much more
> widely used than omnixtend that support cache coherent memory access over a
> network: google "rdma cache coherent"

adding "wishbone" to that and opensparc T1 comes up
https://www.oracle.com/technetwork/systems/opensparc/opensparc-internals-book-1500271.pdf

-- 
You are receiving this mail because:
You are on the CC list for the bug.