[libre-riscv-dev] [Bug 298] New: consider using sum-addressed decoder in L1 cache (maybe also L1 I cache)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=298

            Bug ID: 298
           Summary: consider using sum-addressed decoder in L1 cache
                    (maybe also L1 I cache)
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: All
                OS: All
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: programmerjake at gmail.com
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

combines binary adder with address decoder, saving a few gate delays.
https://en.wikipedia.org/wiki/Sum-addressed_decoder
The patents appear to have expired.

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