[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #132 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #131)
> btw don't be afraid to commit unit tests that don't "quotes work quotes".
> 
> when it comes to unit tests, the whole idea is to have
> "things-that-demonstrate-a-need-to-fix-code" rather than "have everything
> absolutely perfect".
> 
> so do go ahead and commit some unit tests that actually break, but you
> expect them to pass at some point in the future.
> 
> i say that because in the past i noticed that you commented out some unit
> tests which "failed".  just leave them to fail, as a reminder.  also
> there's a way to tag them with bugreports (with decorators).
> 
> i'll document this in HDL_workflow.

Actually, I'd decorate them with something like:
import unittest

@unittest.skip("not working yet")
def test_fn():
    body-here

or

@unittest.expectedFailure # FIXME: not working yet
def test_fn():
    body-here


That way, once I add support for GitLab CI we will get a message when one of
the commits fails any of the tests, allowing us to more quickly detect that
something unexpectedly broke. If it's filled with a whole bunch of tests that
we know will fail, then that makes the CI nearly worthless because it will
always be filled with a bunch of failures obscuring the ones we care about.

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