[libre-riscv-dev] cache SRAM organisation

[Luke Kenneth Casson Leighton]

On Thursday, March 26, 2020, Staf Verhaegen <staf at fibraservi.eu> wrote:

> (Sorry send to early)
>
>
> > .In theory on a single port SRAM
>
> In theory on a single port SRAM the write data input and the Q data output
> could be on opposite sides of the block but I will make sure that these
> pins are on the same side of the block and close together so you don't need
> much wire to connect a pass-through MUX.


ah fantastic, really appreciated.

that will help keep it small.

l.



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