[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #109 from Michael Nolan <mtnolan2640 at gmail.com> ---
I'm going to try using https://sourceware.org/gdb/wiki/PythonGdb to see if I
can't get something working that way.

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