[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #102 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #98)
> https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/simulator/test_sim.
> py;hb=HEAD
> 
> y'know... the comment "checked this against qemu" got me thinking. this
> looks like it could be used to actually run any of:
> 
> * qemu

what do you think, michael: does firing off qemu to run those same
(tiny) binaries sound practical?

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