[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=257

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/minerva/cache.py;hb=HEAD

they set the cache up to be a maximum of 2-way.  however that's not the same as
the number of read/write ports.  arg.

ok i found a diagram which explains it:
https://libre-riscv.org/3d_gpu/architecture/set_associative_cache.jpg

it shouuuld be relatively straightforward to augment that to be dual-ported,
although let's not do that straight away.

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