[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #82 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Michael Nolan from comment #79)
> Ok, so I've got an instruction, for example: 
> add 4, 16, 7
> which gets assembled to:
> 0x7c903a14
> or:
> value:   0111 1100 1001 0000 0011 1010 0001 0100
> field:    oooo oott ttta aaaa       mmm mmmm mmm
> number:  0123 4567 8901 2345 6789 0123 4567 8901
> 
> o: Opcode = 31
> m: Opcode minor = 266/0b0100001010 - ADD - form XO
> t: RT = 0b00100 = 4
> 
> This all looks right, right?
> 
> Somehow the decoder is getting write_reg=8 (write_reg should be RT) out of
> this, and I'm not sure how. 0b00100 is 4 regardless of bit ordering...
> 
> I double checked, and pdecoder.dec.RT is 
> SignalBitRange([(0, 6), (1, 7), (2, 8), (3, 9), (4, 10)])
> which seems right. Any idea of where to look?

Oh I see. It's bit reversing the whole word

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