[libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

Immanuel, Yehowshua U yimmanuel3 at gatech.edu
Sun Mar 15 19:20:03 GMT 2020

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Or, is the internal format some sort of intermediate that both RISCV and POWER instructions map down to?

Yehowshua

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