[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #61 from Jacob Lifshay <programmerjake at gmail.com> ---
We should check the spec to see what its conventions are -- some use bit 0 as
MSB, some as LSB. Also, the memory interface may or may not byte swap.

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