[libre-riscv-dev] IBM releases A2I core VHDL

[Jacob Lifshay]

On Tue, Jun 30, 2020, 01:57 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Tue, Jun 30, 2020 at 9:50 AM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >
> > On Tue, Jun 30, 2020 at 7:35 AM Lauri Kasanen <cand at gmx.com> wrote:
> > >
> > > Hi,
> > >
> > > https://github.com/openpower-cores/a2i
>
>
> https://github.com/openpower-cores/a2i/blob/master/rel/src/vhdl/work/fuq_sto.vhdl
>
> holy cow.  they did full gate-level design, effectively.
>
> it also looks like the code's been run through a comment-sanitiser,
> which makes it almost impossible to understand.
>

Another option is that what they published is the output of a synthesizer.
It strikes me as quite odd to include the power lines as inputs and outputs
for each logic block, those have always been implicit for languages like
VHDL or Verilog in my experience.

Jacob