[libre-riscv-dev] libresoc memory architecture

[Michael Nolan]

On 6/24/20 11:50 AM, Luke Kenneth Casson Leighton wrote:
> i'm transferring the signal comments over to
> soc.minerva.units.loadstore.LoadStoreUnitInterface.
>
Oh thanks. I'm still working on understanding exactly how the 
LoadStoreUnitInterface works exactly, but I'm making some progress I 
think. What really confused me is that the valid and stall signals are 
both inputs indicating whether the pipeline stages are enabled or 
stalled. I'll continue updating the comments in loadstore.py as I figure 
things out.

--Michael