[libre-riscv-dev] libresoc memory architecture

[Luke Kenneth Casson Leighton]

On Wed, Jun 24, 2020 at 2:24 PM Michael Nolan <mtnolan2640 at gmail.com> wrote:

> > 1) a TestMemoryLoadStoreUnit that contains a TestMemory instance and
> > presents a LoadStoreInterface.

> Ok, this seems reasonably straightforward. I'll give it a go.

star.  a look-ahead towards the integration testing: a
reconfigureable-class that (just like minerva) does runtime-selection
of which type of LoadStoreInterface-compatible "thing" to instantiate
would be good:

class ConfigureableLoadStoreUnit:
    def __init__(self, ifacetype, *args, **kwargs):
        if ifacetype == "testmem":
            self.lsi = TestMemoryLoadStoreUnit(*args, **kwargs)
        elif ifacetype == "bare_wb":
            self.lsi = BareLoadStoreUnit(*args, **kwargs)
        elif ifacetype == "cache_wb":
            self.lsi = CacheLoadStoreUnit(*args, **kwargs)

although from experience that might be better to use pspec which
contains parameters and so is a bit less of a mess when it comes to
setting up.

l.