[libre-riscv-dev] libresoc memory architecture

[Luke Kenneth Casson Leighton]

urr, yuk.  here you can see that actually what Decoder is doing is
actually *broadcasting* requests onto the sub-buses.



https://git.libre-soc.org/?p=nmigen-soc.git;a=blob;f=nmigen_soc/wishbone/bus.py;hb=HEAD#l306

 306             for sub_map, (sub_pat, sub_ratio) in
self._map.window_patterns():
 307                 sub_bus = self._subs[sub_map]
 308
 309                 m.d.comb += [
 310                     sub_bus.adr.eq(self.bus.adr << log2_int(sub_ratio)),
 311                     sub_bus.dat_w.eq(self.bus.dat_w),