[libre-riscv-dev] daily kan-ban update 15jun2020

[Yehowshua]

> 
> what i might do for now is just drop in a small SRAM just to get
> something working.

You might already know, but you can do an SRAM like so:
**should also map to ECP5 BRAM blocks in Yosys

```
from nmigen import Memory
gprf = Memory(width=32, depth=32)
gprf_rp1 = gprf.read_port()
gprf_rp2 = gprf.read_port()
gprf_wp  = gprf.write_port()
```

https://github.com/lambdaconcept/minerva/blob/master/minerva/core.py#L227

Yehowshua