[libre-riscv-dev] daily kan-ban update 05jun2020

[Luke Kenneth Casson Leighton]

yesterday:

* got surprisingly far very quickly with the unit test for the simple
core.  all integer comparisons of the regfile work fine.
* worked with Cole on the TRAP pipeline. there is oddness in microwatt from
SPRs being passed through reg data lines, had to sort that out

today:

* slept for several hours. very long day yesterday.
* tried tracking down Condition Register discrepancies in the read/write
side to CR regfile. related to bit ordering.
* go over LDST buffer to be able to help Tobias.
* start thinking how to pull in LDSTCompUnit into the pipeline tests.




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