[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=353

--- Comment #37 from Michael Nolan <mtnolan2640 at gmail.com> ---
Aha, I knew something was fishy. The inputs should have been AnySeq not
AnyConst. Because it's a sequential circuit, they should be able to change on
any cycle (to be able to read or write and such)

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