[libre-riscv-dev] Named Records in nMigen

[Jock Tanner]

Yehowshua,

In case you or anybody else come back to this question eventually: it
is possible to define a subsignal using built-in `slice()`. For
example, if the bits 4-7 of your instruction defines a source register,
you can do something similar to

  INSTR_SRC = slice(4, 8)

  # ...

  m.d.comb += self.src_reg.eq(instr[INSTR_SRC])

... or even wrap slices in standard `enum.Enum`:

  class InstrFormat(Enum):
    dst = slice(4)
    src = slice(4, 8)
    # ...

  m.d.comb += self.src_reg.eq(instr[InstrFormat.src])

Hope it helps.

On Mon, 2020-06-01 at 02:33 -0400, Yehowshua wrote:
> Actually - scratch that - I got it working fine.
> 
> Yehowshua
> 
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