[libre-riscv-dev] multi issue

[Luke Kenneth Casson Leighton]

On Fri, May 31, 2019 at 12:08 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> On Thu, May 30, 2019, 16:04 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > On Thu, May 30, 2019 at 11:58 PM Jacob Lifshay <programmerjake at gmail.com>
> > wrote:
> >
> > > we will additionally need to decide which variety of long instruction
> > > encoding we will support: the encoding in the original spec or the new
> > > encoding proposed by clifford wolf.
> >
> >  both, by using the mvendorid-marchid-isamux scheme that i created
> > last year.  the isamux scheme is identical to that used by PowerPC to
> > dynamically swap from big-endian to little-endian, generalised.
> >
> >  that's if there are any instructions in the extended format that we
> > actually need.
> >
> Our custom 48 and 64-bit instructions will need to fit in the encoding
> scheme.

 no, it doesn't.  that's what mvendorid-marchid-isamux is very
specifically designed *not* to be forced to have to conform to.

the discussion was documented here:
https://libre-riscv.org/isa_conflict_resolution/

> > > slots then can be then enqueued into the instruction queue.
> >
> that was intended to be the pre-vectorization queue.

 oh ok.

 one trick is to map 16-bit to 32-bit equivalents.  it gives a uniform
instruction size.

l.