[libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=99

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
btw you'll see these puzzling things in each stage:

   with m.If(~self.i.out_do_z):

these are activated back in the special-cases:

        # if b is zero return Inf
        with m.Elif(b1.is_zero):
            m.d.comb += self.o.out_do_z.eq(1)
            m.d.comb += self.o.z.inf(sabx)

such that the result (which is already valid, as a special-case)
can propagate down the (entire) pipeline, unmodified.

this because i haven't worked out early-out bypassing, yet.

hmm must write a separate bugreport as we need cancellation (go_die).

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