[libre-riscv-dev] [Bug 78] IEEE754 FP "div" needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=78

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)

> > FSQRT and ISQRT are definitely going to be done as pipelines, jacob knows
> > if we need FDIV to be pipelined.
> having a pipelined fdiv is more important than sqrt or rsqrt, since
> divisions are much more common (every pixel needs at least 1 division)

rats.  ok i should be able to knock something together quite quickly,
however it's going to need a whopping *fourteen* stages even if done as
a 4x combinatorial chain of 14x pipelines.

or it could be *26* pipelines stages of 2x combinatorial blocks.  that's just
for 32-bit FP.  64-bit FP would be a staggering 56 pipeline stages.  luckily
we don't need that, as the focus isn't 64-bit.

will raise a separate bugreport for this one.

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