[libre-riscv-dev] spike simple-v implementation, refinement needed

[Luke Kenneth Casson Leighton]

https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/xfWAqSnNng4/QrbDUYi1AQAJ

this discussion highlights an issue with SV.  the plan was: not to
have any new instructions. the discussion shows that this *may* be
unavoidable, or that the loops would require an extra instruction:

instead of:

loop:
 setvl t0, a0, 4 # vl = t0 = min(min(mvl, 4, n))
 ld    a3, a1    # load 4 registers a3-6 from x
 slli  t1, t0, 3 # t1 = vl * 8 (in bytes)
 ld    a7, a2    # load 4 registers a7-10 from y

it would be:

loop:
 setvl a0, 4 # vl= min(min(mvl, 4, a0))
 getvl t0 # t0 = vl
 ld    a3, a1    # load 4 registers a3-6 from x
 slli  t1, t0, 3 # t1 = vl * 8 (in bytes)
 ld    a7, a2    # load 4 registers a7-10 from y

this is not really desirable (the extra instruction) although it could
reasonably be claimed that macro-op fusion could take care of it.

one possibility: have a separate CSR that sets a register which is to
be allocated *AS* vl.

i'll have to think about this and raise some further discussion.

l.